HAL SMBUS constants migration ¶
This section provides information about the HAL SMBUS constants migration .
HAL SMBUS error code constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define HAL_SMBUS_ERROR_NONE
#define HAL_SMBUS_ERROR_BERR
#define HAL_SMBUS_ERROR_ARLO
#define HAL_SMBUS_ERROR_ACKF
#define HAL_SMBUS_ERROR_OVR
#define HAL_SMBUS_ERROR_BUSTIMEOUT
#define HAL_SMBUS_ERROR_ALERT
#define HAL_SMBUS_ERROR_PECERR
#define HAL_SMBUS_ERROR_INVALID_CALLBACK
#define HAL_SMBUS_ERROR_INVALID_PARAM
#define HAL_SMBUS_ERROR_HALTIMEOUT
#define HAL_SMBUS_ERROR_TIMEOUT
|
#define HAL_SMBUS_ERROR_NONE
#define HAL_SMBUS_ERROR_BERR
#define HAL_SMBUS_ERROR_ARLO
#define HAL_SMBUS_ERROR_ACKF
#define HAL_SMBUS_ERROR_OVR
#define HAL_SMBUS_ERROR_BUSTIMEOUT
#define HAL_SMBUS_ERROR_ALERT
#define HAL_SMBUS_ERROR_PECERR
Removed; these kinds of logical errors are reported by direct function return. |
Related concept:
HAL SMBUS state code constants ¶
|
HAL1 |
HAL2 |
|---|---|
|
In HAL1, the SMBUS state implementation uses
|
In HAL2, each possible combination of states is explicitly defined as unique enumerator. |
#define HAL_SMBUS_STATE_RESET
#define HAL_SMBUS_STATE_MASTER_BUSY_TX
#define HAL_SMBUS_STATE_MASTER_BUSY_RX
#define HAL_SMBUS_STATE_LISTEN
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX
#define HAL_SMBUS_STATE_BUSY
#define HAL_SMBUS_STATE_READY
|
typedef enum
{
HAL_SMBUS_STATE_RESET
HAL_SMBUS_STATE_INIT
HAL_SMBUS_STATE_IDLE
HAL_SMBUS_STATE_TX
HAL_SMBUS_STATE_RX
HAL_SMBUS_STATE_LISTEN
HAL_SMBUS_STATE_TX_LISTEN
HAL_SMBUS_STATE_RX_LISTEN
HAL_SMBUS_STATE_ABORT
} hal_smbus_state_t;
|
Related concept:
HAL SMBUS addressing modes constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_ADDRESSINGMODE_10BIT
#define SMBUS_ADDRESSINGMODE_7BIT
|
Removed; the choice between 7‑bit and 10‑bit addressing, which is available in the I²C protocol, is not relevant in the SMBus protocol. SMBUS is restricted to 7‑bit addressing , simplifying and standardizing communication between devices. |
HAL SMBUS analog filter states constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_ANALOGFILTER_DISABLE
#define SMBUS_ANALOGFILTER_ENABLE
|
Removed; in HAL2 the SMBUS analog filter is managed by unitary functions in the HAL layer. hal_status_t HAL_SMBUS_EnableAnalogFilter(hal_smbus_handle_t *hsmbus)
hal_status_t HAL_SMBUS_DisableAnalogFilter(hal_smbus_handle_t *hsmbus)
|
HAL SMBUS autonomous mode states constants ¶
|
HAL1 |
HAL2 |
|---|---|
|
In HAL1, the SMBUS autonomous mode is a member of the
#define SMBUS_AUTO_MODE_DISABLE
#define SMBUS_AUTO_MODE_ENABLE
|
Removed; in HAL2, the SMBUS autonomous mode is managed by unitary functions in the HAL layer. For more details, refer to HAL SMBUS autonomous mode configuration type definition. hal_status_t HAL_SMBUS_AM_EnableTrigger(hal_smbus_handle_t *hsmbus);
hal_status_t HAL_SMBUS_AM_DisableTrigger(hal_smbus_handle_t *hsmbus);
|
HAL SMBUS direction types constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_DIRECTION_RECEIVE
#define SMBUS_DIRECTION_TRANSMIT
|
typedef enum
{
HAL_SMBUS_SLAVE_DIRECTION_TRANSMIT
HAL_SMBUS_SLAVE_DIRECTION_RECEIVE
} hal_smbus_slave_xfer_direction_t;
|
Related concept:
HAL SMBUS dual address states constants ¶
|
HAL1 |
HAL2 |
|---|---|
|
In HAL1, the SMBUS dual addressing mode is a member of the
#define SMBUS_DUALADDRESS_DISABLE
#define SMBUS_DUALADDRESS_ENABLE
|
Removed; in HAL2, the SMBUS dual addressing mode is managed by unitary functions in the HAL layer. hal_status_t HAL_SMBUS_EnableOwnAddress2(hal_smbus_handle_t *hsmbus);
hal_status_t HAL_SMBUS_DisableOwnAddress2(hal_smbus_handle_t *hsmbus);
|
HAL SMBUS fast mode plus enable/disable constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_FASTMODEPLUS_DISABLE
#define SMBUS_FASTMODEPLUS_ENABLE
|
typedef enum
{
HAL_SMBUS_FAST_MODE_PLUS_DISABLED
HAL_SMBUS_FAST_MODE_PLUS_ENABLED
} hal_smbus_fast_mode_plus_status_t;
|
Related concept:
HAL SMBUS fast mode plus I2C peripherals constants ¶
|
HAL1 |
HAL2 |
|---|---|
|
In HAL1 the SMBUS enable fast mode plus and disable have been managed by APIs:
The parameter
|
In HAL2 the SMBUS enable fast mode plus and disable are managed by APIs:
The selection of pin is managed by the SYSCFG driver
The parameter
|
#define SMBUS_FMP_NOT_SUPPORTED
#define SMBUS_FASTMODEPLUS_I2C1
#define SMBUS_FASTMODEPLUS_I2C2
#define SMBUS_FASTMODEPLUS_I2C3
#define SMBUS_FASTMODEPLUS_I2C4
#define SMBUS_FASTMODEPLUS_PA10
#define SMBUS_FASTMODEPLUS_PA9
#define SMBUS_FASTMODEPLUS_PB6
#define SMBUS_FASTMODEPLUS_PB7
#define SMBUS_FASTMODEPLUS_PB8
#define SMBUS_FASTMODEPLUS_PB9
|
hal_status_t HAL_SMBUS_EnableFastModePlus(hal_smbus_handle_t *hsmbus);
hal_status_t HAL_SMBUS_DisableFastModePlus(hal_smbus_handle_t *hsmbus);
|
HAL SMBUS transfer options constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_FIRST_FRAME
#define SMBUS_NEXT_FRAME
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC
#define SMBUS_LAST_FRAME_NO_PEC
#define SMBUS_FIRST_FRAME_WITH_PEC
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC
#define SMBUS_LAST_FRAME_WITH_PEC
#define SMBUS_OTHER_FRAME_NO_PEC
#define SMBUS_OTHER_FRAME_WITH_PEC
#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC
#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC
|
typedef enum
{
HAL_SMBUS_XFER_FIRST_FRAME
HAL_SMBUS_XFER_NEXT_FRAME
HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_NO_PEC
HAL_SMBUS_XFER_LAST_FRAME_NO_PEC
HAL_SMBUS_XFER_FIRST_FRAME_WITH_PEC
HAL_SMBUS_XFER_FIRST_AND_LAST_FRAME_WITH_PEC
HAL_SMBUS_XFER_LAST_FRAME_WITH_PEC
HAL_SMBUS_XFER_OTHER_FRAME_NO_PEC
HAL_SMBUS_XFER_OTHER_FRAME_WITH_PEC
HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_NO_PEC
HAL_SMBUS_XFER_OTHER_AND_LAST_FRAME_WITH_PEC
} hal_smbus_xfer_opt_t;
|
Related concept:
HAL SMBUS flags constants ¶
The listed defines in HAL1 are used by : HAL SMBUS get flag, and HAL SMBUS clear flags.
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_FLAG_MASK
#define SMBUS_FLAG_SMBALERT
#define SMBUS_FLAG_SMBDEFAULT
#define SMBUS_FLAG_SMBHOST
#define SMBUS_FLAG_TXE
#define SMBUS_FLAG_TXIS
#define SMBUS_FLAG_RXNE
#define SMBUS_FLAG_ADDR
#define SMBUS_FLAG_AF
#define SMBUS_FLAG_STOPF
#define SMBUS_FLAG_TC
#define SMBUS_FLAG_TCR
#define SMBUS_FLAG_BERR
#define SMBUS_FLAG_ARLO
#define SMBUS_FLAG_OVR
#define SMBUS_FLAG_PECERR
#define SMBUS_FLAG_TIMEOUT
#define SMBUS_FLAG_ALERT
#define SMBUS_FLAG_BUSY
#define SMBUS_FLAG_DIR
#define SMBUS_FLAG_ADD10
#define SMBUS_FLAG_BTF
#define SMBUS_FLAG_SB
#define SMBUS_FLAG_DUALF
#define SMBUS_FLAG_GENCALL
#define SMBUS_FLAG_TRA
#define SMBUS_FLAG_MSL
|
Removed; use LL_I2C_IsActiveFlag instead.
Removed; use LL_I2C_IsActiveSMBusFlag_ALERT / LL_I2C_ClearSMBusFlag_ALERT instead.
Removed; use LL_I2C_IsActiveFlag instead.
Removed; use LL_I2C_IsActiveFlag instead.
Removed; use LL_I2C_IsActiveFlag / LL_I2C_ClearFlag_TXE instead.
Removed; use LL_I2C_IsActiveFlag instead.
Removed; use LL_I2C_IsActiveFlag instead.
Removed; use LL_I2C_IsActiveFlag / LL_I2C_ClearFlag_ADDR instead.
Removed; use LL_I2C_IsActiveFlag / LL_I2C_ClearFlag_NACK instead.
Removed; use LL_I2C_IsActiveFlag / LL_I2C_ClearFlag_STOP instead.
Removed; use LL_I2C_IsActiveFlag instead.
Removed; use LL_I2C_IsActiveFlag instead.
Removed; use LL_I2C_IsActiveFlag / LL_I2C_ClearFlag_BERR instead.
Removed; use LL_I2C_IsActiveFlag / LL_I2C_ClearFlag_ARLO instead.
Removed; use LL_I2C_IsActiveFlag / LL_I2C_ClearFlag_OVR instead.
Removed; use LL_I2C_IsActiveFlag instead.
Removed; use LL_I2C_IsActiveSMBusFlag_PECERR / LL_I2C_ClearSMBusFlag_PECERR instead.
Removed; use LL_I2C_IsActiveSMBusFlag_TIMEOUT / LL_I2C_ClearSMBusFlag_TIMEOUT instead.
Removed; use LL_I2C_IsActiveSMBusFlag_ALERT / LL_I2C_ClearSMBusFlag_ALERT instead.
Removed; use LL_I2C_IsActiveFlag instead.
Not implemented yet in HAL2.
Not implemented yet in HAL2.
Not implemented yet in HAL2.
Not implemented yet in HAL2.
Not implemented yet in HAL2.
Not implemented yet in HAL2.
Not implemented yet in HAL2.
|
Related concept:
HAL SMBUS general call states constants ¶
|
HAL1 |
HAL2 |
|---|---|
|
In HAL1, the SMBUS general call addressing mode is a member of the
|
Removed; In HAL2, the SMBUS general call addressing mode is managed by unitary functions in the HAL layer. |
#define SMBUS_GENERALCALL_DISABLE
#define SMBUS_GENERALCALL_ENABLE
|
hal_status_t HAL_SMBUS_SLAVE_EnableAckGeneralCall(hal_smbus_handle_t *hsmbus);
hal_status_t HAL_SMBUS_SLAVE_DisableAckGeneralCall(hal_smbus_handle_t *hsmbus);
|
HAL SMBUS generate commands constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_NO_STARTSTOP
#define SMBUS_GENERATE_NO_START_READ
#define SMBUS_GENERATE_NO_START_WRITE
#define SMBUS_GENERATE_STOP
#define SMBUS_GENERATE_START_READ
#define SMBUS_GENERATE_START_WRITE
|
Removed; these constants have been used internally in
|
HAL SMBUS autonomous mode trigger selection constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_TRIG_GRP1
#define SMBUS_TRIG_GRP2
#define SMBUS_GRP1_COMP1_TRG
#define SMBUS_GRP1_COMP2_TRG
#define SMBUS_GRP1_EXTI5_TRG
#define SMBUS_GRP1_EXTI9_TRG
#define SMBUS_GRP1_GPDMA_CH0_TCF_TRG
#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG
#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG
#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG
#define SMBUS_GRP1_LPTIM1_CH1_TRG
#define SMBUS_GRP1_LPTIM2_CH1_TRG
#define SMBUS_GRP1_RTC_ALRA_TRG
#define SMBUS_GRP1_RTC_WUT_TRG
#define SMBUS_GRP2_COMP1_TRG
#define SMBUS_GRP2_COMP2_TRG
#define SMBUS_GRP2_EXTI5_TRG
#define SMBUS_GRP2_EXTI8_TRG
#define SMBUS_GRP2_LPDMA_CH0_TCF_TRG
#define SMBUS_GRP2_LPDMA_CH1_TCF_TRG
#define SMBUS_GRP2_LPDMA_CH2_TCF_TRG
#define SMBUS_GRP2_LPDMA_CH3_TCF_TRG
#define SMBUS_GRP2_LPTIM1_CH1_TRG
#define SMBUS_GRP2_LPTIM3_CH1_TRG
#define SMBUS_GRP2_RTC_ALRA_TRG
#define SMBUS_GRP2_RTC_WUT_TRG
|
Used internally and do not impact user-level operations.
Used internally and do not impact user-level operations.
typedef enum
{
HAL_SMBUS_AM_TRIG_GRP1_COMP1_OUT
HAL_SMBUS_AM_TRIG_GRP1_COMP2_OUT
HAL_SMBUS_AM_TRIG_GRP1_EXTI5
HAL_SMBUS_AM_TRIG_GRP1_EXTI9
HAL_SMBUS_AM_TRIG_GRP1_GPDMA1_CH0_TC
HAL_SMBUS_AM_TRIG_GRP1_GPDMA1_CH1_TC
HAL_SMBUS_AM_TRIG_GRP1_GPDMA1_CH2_TC
HAL_SMBUS_AM_TRIG_GRP1_GPDMA1_CH3_TC
HAL_SMBUS_AM_TRIG_GRP1_LPTIM1_CH1
HAL_SMBUS_AM_TRIG_GRP1_LPTIM2_CH1
HAL_SMBUS_AM_TRIG_GRP1_RTC_ALRA_TRG
HAL_SMBUS_AM_TRIG_GRP1_RTC_WUT_TRG
HAL_SMBUS_AM_TRIG_GRP2_COMP1_OUT
HAL_SMBUS_AM_TRIG_GRP2_COMP2_OUT
HAL_SMBUS_AM_TRIG_GRP2_EXTI5
HAL_SMBUS_AM_TRIG_GRP2_EXTI8
HAL_SMBUS_AM_TRIG_GRP2_LPDMA1_CH0_TC
HAL_SMBUS_AM_TRIG_GRP2_LPDMA1_CH1_TC
HAL_SMBUS_AM_TRIG_GRP2_LPDMA1_CH2_TC
HAL_SMBUS_AM_TRIG_GRP2_LPDMA1_CH3_TC
HAL_SMBUS_AM_TRIG_GRP2_LPTIM1_CH1
HAL_SMBUS_AM_TRIG_GRP2_LPTIM3_CH1
HAL_SMBUS_AM_TRIG_GRP2_RTC_ALRA_TRG
HAL_SMBUS_AM_TRIG_GRP2_RTC_WUT_TRG
} hal_smbus_am_trig_source_t;
|
Related concept:
HAL SMBUS interrupt types constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_IT_ADDR
#define SMBUS_IT_ADDRI
#define SMBUS_IT_ALERT
#define SMBUS_IT_BUF
#define SMBUS_IT_ERR
#define SMBUS_IT_ERRI
#define SMBUS_IT_EVT
#define SMBUS_IT_NACKI
#define SMBUS_IT_RX
#define SMBUS_IT_RXI
#define SMBUS_IT_STOPI
#define SMBUS_IT_TCI
#define SMBUS_IT_TX
#define SMBUS_IT_TXI
|
Removed; use LL_I2C_EnableIT_ADDR / LL_I2C_DisableIT_ADDR / LL_I2C_IsEnabledIT_ADDR instead.
Removed; use LL_I2C_EnableIT_ADDR / LL_I2C_DisableIT_ADDR / LL_I2C_IsEnabledIT_ADDR instead.
Removed; use LL_I2C_EnableSMBusAlert / LL_I2C_DisableSMBusAlert / LL_I2C_IsEnabledSMBusAlert
Removed; use LL_I2C_EnableIT_BUF / LL_I2C_DisableIT_BUF / LL_I2C_IsEnabledIT_BUF instead.
Removed; use LL_I2C_EnableIT_ERR / LL_I2C_DisableIT_ERR / LL_I2C_IsEnabledIT_ERR instead.
Removed; use LL_I2C_EnableIT_ERR / LL_I2C_DisableIT_ERR / LL_I2C_IsEnabledIT_ERR instead.
Removed; use LL_I2C_EnableIT_EVT / LL_I2C_DisableIT_EVT / LL_I2C_IsEnabledIT_EVT instead.
Removed; use LL_I2C_EnableIT_NACK / LL_I2C_DisableIT_NACK / LL_I2C_IsEnabledIT_NACK instead.
Removed; use LL_I2C_EnableIT_RX / LL_I2C_DisableIT_RX / LL_I2C_IsEnabledIT_RX instead.
Removed; use LL_I2C_EnableIT_RX / LL_I2C_DisableIT_RX / LL_I2C_IsEnabledIT_RX instead.
Removed; use LL_I2C_EnableIT_STOP / LL_I2C_DisableIT_STOP / LL_I2C_IsEnabledIT_STOP instead.
Removed; use LL_I2C_EnableIT_TC / LL_I2C_DisableIT_TC / LL_I2C_IsEnabledIT_TC instead.
Removed; use LL_I2C_EnableIT_TX / LL_I2C_DisableIT_TX / LL_I2C_IsEnabledIT_TX instead.
Removed; use LL_I2C_EnableIT_TX / LL_I2C_DisableIT_TX / LL_I2C_IsEnabledIT_TX instead.
|
HAL SMBUS no stretch states constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_NOSTRETCH_DISABLE
#define SMBUS_NOSTRETCH_ENABLE
|
Removed; The SMBUS protocol is based on clock stretching, and it is always enabled |
HAL SMBUS own address 2 mask constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_OA2_NOMASK
#define SMBUS_OA2_MASK01
#define SMBUS_OA2_MASK02
#define SMBUS_OA2_MASK03
#define SMBUS_OA2_MASK04
#define SMBUS_OA2_MASK05
#define SMBUS_OA2_MASK06
#define SMBUS_OA2_MASK07
|
typedef enum
{
HAL_SMBUS_OWN_ADDR2_NOMASK
HAL_SMBUS_OWN_ADDR2_MASK01
HAL_SMBUS_OWN_ADDR2_MASK02
HAL_SMBUS_OWN_ADDR2_MASK03
HAL_SMBUS_OWN_ADDR2_MASK04
HAL_SMBUS_OWN_ADDR2_MASK05
HAL_SMBUS_OWN_ADDR2_MASK06
HAL_SMBUS_OWN_ADDR2_MASK07
} hal_smbus_own_addr2_mask_t;
|
Related concept:
HAL SMBUS PEC states constants ¶
|
HAL1 |
HAL2 |
|---|---|
|
Removed; In HAL2 the SMBUS packet error check is managed by unitary functions in the HAL layer. |
|
#define SMBUS_PEC_DISABLE
#define SMBUS_PEC_ENABLE
|
hal_status_t HAL_SMBUS_EnablePacketErrorCheck(hal_smbus_handle_t *hsmbus)
hal_status_t HAL_SMBUS_DisablePacketErrorCheck(hal_smbus_handle_t *hsmbus)
|
HAL SMBUS peripheral modes constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP
|
typedef enum
{
HAL_SMBUS_PERIPHERAL_MODE_HOST
HAL_SMBUS_PERIPHERAL_MODE_SLAVE
HAL_SMBUS_PERIPHERAL_MODE_SLAVE_ARP
} hal_smbus_mode_t;
|
Related concept:
HAL SMBUS reload mode constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_SOFTEND_MODE
#define SMBUS_RELOAD_MODE
#define SMBUS_AUTOEND_MODE
#define SMBUS_SENDPEC_MODE
|
Removed; these constants have been used internally in
|
HAL SMBUS trigger types constants ¶
|
HAL1 |
HAL2 |
|---|---|
#define SMBUS_TRIG_POLARITY_RISING
#define SMBUS_TRIG_POLARITY_FALLING
|
typedef enum
{
HAL_SMBUS_AM_TRIG_RISING
HAL_SMBUS_AM_TRIG_FALLING
} hal_smbus_am_trig_polarity_t;
|
Related concept: